Double precision division circuit and method for digital signal processor
US5426600A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Sep 27, 1993 |
| Grant date | Jun 20, 1995 |
| Priority date | — |
| Expiry date | Sep 27, 2013 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2207/5352
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An arithmetic operation execution unit includes a plurality of 2N bit data registers and an arithmetic logic unit (ALU). The execution unit is coupled to data busses each having a data path width of N bits for transferring data to and from the data registers. An XOR gate and inverter gate are provided for computing a quotient bit QB and a next ALU operation command bit QOP. A bit processing unit (BPU) shifts the QB bit generated during the previous instruction cycle into an output register during each instruction cycle. The execution unit responds to three predefined division instructions by configuring the ALU, BPU and XOR gate to perform three distinct functions. A first instruction performed for each division computation computes initial QB and QOP values. A second instruction is executed multiple times. Each execution of the second instruction computes one quotient bit QB, shifts a quotient bit computed in the prior instruction cycle into the least significant bit of a destination register, and also computes a QOP value that determines the next ALU operation to be performed. A final instruction shifts the last computed quotient bit into the destination register and also adds th…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.