Dynamic RAM and information processing system using the same
US5426603A · kind A · utility
110Cited by
0References
14Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jan 25, 1994 |
| Grant date | Jun 20, 1995 |
| Priority date | — |
| Expiry date | Jan 25, 2014 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/4091
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A dynamic RAM is provided using a sense amplifier compensating for the disparities of characteristics for paired MOSFET's. With this arrangement parasitic capacitance of the bit lines can be increased to be at least 20 times the capacitance of the memory cells. Each bit line is bisected by a switch MOSFET and is disconnected thereby as needed. A plurality of sets of memory arrays are furnished, each including a switch MOSFET for interconnecting common source lines to which the sense amplifier is connected. This permits recycling of the charges of the common source lines.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.