Semiconductor memory device
US5426605A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Aug 18, 1993 |
| Grant date | Jun 20, 1995 |
| Priority date | — |
| Expiry date | Aug 18, 2013 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D86/01
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor memory device includes an array of rows and columns of field effect transistors (FETs) which provide memory locations. The FET gate electrodes in each row are connected to a respective row conductor and the FET first and second main electrodes in each column are connected to respective adjacent column conductors so that the second main electrodes in one column are connected to the first electrodes of the FETs in any adjacent column. Circuitry is provided for storing data at and reading data from the memory locations. The circuitry stores data at a desired memory location by applying a first predetermined voltage V.sub.g.sup.W to a selected row conductor and a second predetermined voltage V.sub.d.sup.W to a selected column conductor for establishing within each FET which has its gate electrode connected to the selected row conductor and one main electrode connected to the selected column conductor an electric field for causing a change in the current conduction characteristics of the part of its conduction channel region adjacent the selected column conductor when the difference between the first and second predetermined voltages exceeds a critical voltage so that da…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.