Interference compensating circuit including a matched filter followed by a median filter
US5426670A · kind A · utility
18Cited by
9References
12Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jul 15, 1993 |
| Grant date | Jun 20, 1995 |
| Priority date | — |
| Expiry date | Jul 15, 2013 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04B1/7093
- WIPO fieldTelecommunications
- WIPO sectorElectrical engineering
Abstract
A circuit arrangement is disclosed for reducing the adverse effects of interference in a signal of interest. The circuit arrangement includes a matched filter for receiving the signal of interest and a median filter coupled to the output of the matched filter. The median filtered output signal of the matched filter is utilized to remove interference, to calculate the threshold level, or to estimate the interference level at the output of the matched filter.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.