3-1 Arithmetic logic unit for simultaneous execution of an independent or dependent add/logic instruction pair
US5426743A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jan 24, 1994 |
| Grant date | Jun 20, 1995 |
| Priority date | — |
| Expiry date | Jan 24, 2014 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/30029
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A high speed three-to-one data dependency collapsing ALU can be used to support multiple issue of instructions. The computing apparatus supports multiple issue of instructions it is useful in CISC, superscalar, superscalar RISC, etc. type computer designs. The concept of the ALU is presented along with a detailed description of a design. The apparatus allows the execution of any combination of two independent or dependent arithmetic or logical instructions in a single machine cycle. The 3-1 collapsing ALU structure has a 3-2 carry save adder (CSA); and a 2-1 control arithmetic logic unit (CALU) coupled for an input from the carry save adder; and a first pre-adder logic block coupled with an output to the control arithmentic logic unit; and a control generator; and a second controlled logic block coupled to receive an input from said control generator and having its output coupled to said control arithmetic logic unit. Instructions have an add/logical combinatorial operation which combines all four of the combinations: add-add, add-logical, logical-add, and logical-logical functions; and wherein two or more disassociated ALU operations are specified by a single interlock collapsing …
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.