Semiconductor device including clock selection circuitry selecting between high and low frequency clock signals for reduced power consumption
US5426755A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jun 25, 1992 |
| Grant date | Jun 20, 1995 |
| Priority date | — |
| Expiry date | Jun 25, 2012 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/1078
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor device and an electronic apparatus with the semiconductor device incorporated therein, include a sense amplifier so that a storage device can be read at a high speed and at a low speed, whereby low power consumption may be realized driving low speed reading. When a high speed mode is set and a read instruction is given, the sense amplifier is driven to send out a signal of a bit line to a data bus through the sense amplifier, while when a low speed mode is set and a read instruction is given, a sense amplifier is brought into a non-driven state to send out a signal of a bit line to a data bus without going through the sense amplifier. The semiconductor device may also include a clock control circuit and a clock selection circuit for selecting a high frequency clock signal when the high speed mode is set and for selecting a low frequency clock signal when the low speed mode is set.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.