Multiprocessor cache abitration
US5426765A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Apr 13, 1994 |
| Grant date | Jun 20, 1995 |
| Priority date | — |
| Expiry date | Apr 13, 2014 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/18
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for arbitrating between processor and host bus snoop accesses to a cache subsystem in a multiprocessor system where the processor does not allow for processor cycle aborts. When a processor access and a snoop access both occur and no tag access or tag modify cycle is currently being performed, the snoop access is given priority over the processor access. After an initial arbitration, if any, the processor and snoop accesses alternate tag access if both processor and snoop accesses are active. This balances any wait states incurred between the processor and the host bus and ensures that neither bus is locked out by continual accesses by the other. In addition, tag modify cycles are generally run immediately after the tag access cycles that initiate them.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.