Single PAL circuit generating system clock and control signals to minimize skew
US5426772A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Aug 16, 1993 |
| Grant date | Jun 20, 1995 |
| Priority date | — |
| Expiry date | Aug 16, 2013 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/22
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The invention is for improving the performance of a microprocessor system by reducing the skew between the system clock and critical control signals. Reduction in this skew reduces or eliminates the need for waitstates on data accesses to random access memory devices thereby improving system performance. A clock is programmed to function as an asynchronous state machine to generate the clock signals and the memory device chip select. A clock source from an oscillator is input to the PAL. This clock source is buffered by the and presented at the outputs as the system clock. The memory device chip select is also generated inside this using the source clock and other signals generated inside the PAL.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.