Phase locked loop with low power feedback path and method of operation
US5428317A · kind A · utility
64Cited by
1References
8Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 6, 1994 |
| Grant date | Jun 27, 1995 |
| Priority date | — |
| Expiry date | Sep 6, 2014 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/18
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A phase locked loop (10) has a first (24) and a second (28) feedback path by which a generated clock signal may be phase and frequency matched to an input reference clock signal. The two feedback paths are delay matched so either one may be used to maintain "PLL lock." However, the first path consumes significantly less power than the second path. Control circuitry (22) selects which path is fed back through a multiplexer (126) and disables the second path when the path is not needed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.