Six transistor dynamic content addressable memory circuit
US5428564A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Aug 3, 1992 |
| Grant date | Jun 27, 1995 |
| Priority date | — |
| Expiry date | Aug 3, 2012 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C15/043
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A content addressable memory cell includes six transistors connected together to perform memory read, memory write, and matching operations. This cell has the ability to perform typical memory write and memory read operations as well as the capability of signalling whether or not its stored data matches data that is being searched for. A cross-coupling scheme is used in the memory cell so that a high potential will always be stored on the gate of a transistor whose source is at ground. This cross-coupling scheme increases the amount of charge stored on the storage transistor and decreases the required frequency of refresh operations. In addition to the transistors configured to store data, an additional transistor configured as a diode is used as a rapid discharge path to maximize the efficiency of the cell during a read operation. During a match operation another transistor is utilized to discharge the Match line quickly in the event the stored data does not match the data that is being searched for.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.