Scannable interface to nonscannable microprocessor
US5428623A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jul 1, 1993 |
| Grant date | Jun 27, 1995 |
| Priority date | — |
| Expiry date | Jul 1, 2013 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/2236
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A diagnostic system for diagnosing states of circuit elements is described, wherein scannable circuits can be scanned without disturbing the state of unscannable circuits or violating protocols of busses on which unscannable devices are attached. One unscannable device is a standardized microprocessor. A processor interface circuit is coupled between the microprocessor and scannable processor circuits, via a processor bus, to insulate the scannable processor circuits from the unscannable microprocessor. The processor interface circuit is also scannable, including memory elements which affect the bus, by preventing a scan when the bus is in use. A scan is prevented through the use of a maintenance request signal from a scan controller to the processor interface circuit, and one or more maintenance approval signals from the processor interface circuit to the scan controller.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.