Modular implementation for a parallelized key equation solver for linear algebraic codes
US5428628A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Sep 27, 1993 |
| Grant date | Jun 27, 1995 |
| Priority date | — |
| Expiry date | Sep 27, 2013 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M13/151
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Apparatus and method for implementing a parallelized algorithm for solving the key equation for the decoding of a linear algebraic code. Circuitry implements two computation sequences. One of these executes three multiplication operations and the other executes five multiplication operations, 2t iterations of these two sequences being required to decode t symbols in error. These sequences are coupled such that during each successive 2t iterations, four multiplication operations are executed simultaneously in pairs, the fifth multiplication operation in the other sequence being paired with a multiplication operation in the next iteration of the one sequence. During one of the paired multiplication operations an inverse table look up operation is executed, and during another of the multiplication operations an addition operation is executed. Two consecutive executions of the other sequence are prevented.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.