Two's complement pulse width modulator and method for pulse width modulating a two's complement number
US5428639A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Feb 25, 1994 |
| Grant date | Jun 27, 1995 |
| Priority date | — |
| Expiry date | Feb 25, 2014 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K7/08
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A pulse width modulator (PWM) (20) receives a two's complement input number and separates a sign bit from remaining less significant bits. The PWM converts these bits into an unsigned number in dependence on the sign bit. A comparator (41) provides a compare output signal in response to an output of a counter (30) equaling the unsigned number. An output circuit (25) provides first and second pulse width modulated signals for a length of time determined by the output of the comparator (41) in dependence on whether the sign bit indicates a positive or negative sign. In one embodiment, the PWM (20) converts a negative two's complement number to the unsigned number by one's complementing the least significant bits, and the output circuit (25) keeps the second pulse width modulated signal active for one additional clock cycle to fully convert to two's complement form, without the need for a carry operation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.