Method and apparatus for disabling and restarting clocks
US5428765A · kind A · utility
11Cited by
7References
26Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Aug 12, 1993 |
| Grant date | Jun 27, 1995 |
| Priority date | — |
| Expiry date | Aug 12, 2013 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D30/50
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The ability to stop a clock in a CMOS peripheral device or other CMOS IC, and reliably restart it based on an asynchronous event, provides the basis for considerable power savings. In a computer system 20 an interface component 10 has a clock restart circuit 100. The restart circuit 100 includes a series of D-type CMOS flip-flops (110, 112, 118) that are initially set in their zero state. A logic OR gate 120 receives the microprocessor clock and the complimentary output of the last flip-flop to provide a reliable, restarted clock signal for the interface component 10 and its peripherals 26.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.