Single-chip microcontroller with efficient peripheral testability
US5428770A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Aug 31, 1993 |
| Grant date | Jun 27, 1995 |
| Priority date | — |
| Expiry date | Aug 31, 2013 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/2733
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A single-chip microcontroller (30) includes a central processing unit (CPU) (31) and several memory-mapped peripherals (32, 33, 34, 35) connected to internal address (37) and data (38) buses. The microcontroller (30) includes a test port (40) for receiving test data and providing the test data to the address (37) and data (38) buses to access the memory-mapped peripherals (32, 33, 34, 35) directly. The microcontroller (30) thus allows testing of the memory-mapped peripherals (32, 33, 34, 35) without CPU overhead, significantly reducing test time. The test port (40) includes a shift register (44) which selectively updates address high, address low, and data fields using the test data so that a field need not be re-entered if it doesn't change between test cycles. The test port (40) receives the test data and test control signals via signal lines shared with a general purpose input/output (GPIO) port (33) and requires only one independent control signal line.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.