Method and apparatus for a unified parallel processing architecture
US5428803A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jul 10, 1992 |
| Grant date | Jun 27, 1995 |
| Priority date | — |
| Expiry date | Jul 10, 2012 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F15/17381
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A unified parallel processing architecture connects together an extendible number of clusters of multiple numbers of processors to create a high performance parallel processing computer system. Multiple processors are grouped together into four or more physically separable clusters, each cluster having a common cluster shared memory that is symmetrically accessible by all of the processors in that cluster; however, only some of the clusters are adjacently interconnected. Clusters are adjacently interconnected to form a floating shared memory if certain memory access conditions relating to relative memory latency and relative data locality can create an effective shared memory parallel programming environment. A shared memory model can be used with programs that can be executed in the cluster shared memory of a single cluster, or in the floating shared memory that is defined across an extended shared memory space comprised of the cluster shared memories of any set of adjacently interconnected clusters. A distributed memory model can be used with any programs that are to be executed in the cluster shared memories of any non-adjacently interconnected clusters. The adjacent interconnec…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.