Intra-LSI clock distribution circuit
US5430397A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jan 26, 1994 |
| Grant date | Jul 4, 1995 |
| Priority date | — |
| Expiry date | Jan 26, 2014 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K5/1506
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An intra-LSI clock distribution circuit which includes a main distribution circuit, a plurality of intra-block clock distribution circuitries, feedback wires provided in association with each of blocks and each connected to one of plural block-based clock signal wires within the associated block and the intra-block distribution circuitry of the associated block for feeding back the intra-block clock signal distributed to a given one of circuit elements connected to the intra-block clock signal wires to the intra-block clock distribution circuitry of that block. The intra-block clock distribution circuitry in each of the blocks responds to the block-destined clock signal supplied to the associated block via one of the block-based clock signal wires connected thereto and the intra-block clock signals fed back via the feedback wires in the associated block to thereby generate a plurality of intra-block clock signals having respective phases which depend on differences in phase between the block-destined clock signal and the fed-back intra-block clock signals.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.