An EEPROM Circuit, a memory device having the EEPROM circuit and an IC card having the EEPROM circuit
US5430675A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Oct 13, 1993 |
| Grant date | Jul 4, 1995 |
| Priority date | — |
| Expiry date | Oct 13, 2013 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/10
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In an EEPROM, source electrodes S of memory cell transistors MT1 to MTn are grounded, via transistors MG1 to MGn. The source electrodes S are separated from each other so as to maintain the source electrode S of each of the memory cell transistors MT1 to MTn at an open state, even when a leak path is formed by the memory cell transistor MTi in the written state (low threshold voltage). In the EEPROM, an EPROM circuit in which the write operation can be continuously performed without the erase operation can be obtained. Further, an EEPROM circuit having the nonerasable region (the region which functions as the EPROM) and the erasable region (the region which functions as the EEPROM) can be also provided.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.