Method of and circuitry for detecting synchronism failure of two word sequences
US5430746A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Nov 8, 1993 |
| Grant date | Jul 4, 1995 |
| Priority date | — |
| Expiry date | Nov 8, 2013 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L7/043
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A method of and a circuit arrangement for detecting synchronization of two word sequences between a measurement signal and a reference signal. The signals are applied to an exclusive OR-gate comparator whose output produces an error signal which is compared with an error signal shifted by one period. This comparison is effected by an exclusive OR-gate and in the case of coincidence, indicating that the measurement and reference signals are phase-shifted, a new synchronization is enabled. The output of the exclusive OR-gate is an error signal which is time-shifted in a shift register and multiplexer so that the time shifted bit sequence is compared with the bit sequence of the first error signal in a second exclusive OR-gate which is connected to an AND-gate for detecting coincidence and generating a further synchronization signal which is processed through counters, another AND-gate and a flip-flop to produce the synchronization signal which is applied to the reference pattern generated.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.