Circuit for permanently disabling EEPROM programming
US5432741A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Mar 17, 1994 |
| Grant date | Jul 11, 1995 |
| Priority date | — |
| Expiry date | Mar 17, 2014 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/22
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A circuit for programming an EEPROM 42 which is used to provide trim adjustment for an integrated circuit (IC). The programming circuit provides the capability of programming the EEPROM 42 indefinitely, employing interfaces which are available even after the IC is packaged and encapsulated. Furthermore, it provides the manufacturer or enduser the capability of disabling the programming function permanently, to thereby prevent any inadvertent modifications of the EEPROM 42 data. The programming circuit includes a one-bit EEPROM 32, a nonvolatile memory element which retains its programmed logic state whether or not it is powered up. EEPROM 32 is set during final probe test by the application of a voltage to a probe pad 30 coupled to its set input terminal. Probe pad 30 is exposed such that it may be contacted by a probe prior to IC encapsulation, but is inaccessible after encapsulation. So long as EEPROM 32 is set, EEPROM 42 may be modified upon receipt of a unique address from the system data bus followed by programming data for EEPROM 42. When EEPROM 32 is reset, the programming function of EEPROM 42 is permanently disabled. In a first embodiment, EEPROM 32 is reset by setting a p…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.