Non-volatile memory cell having hole confinement layer for reducing band-to-band tunneling
US5432749A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Apr 26, 1994 |
| Grant date | Jul 11, 1995 |
| Priority date | — |
| Expiry date | Apr 26, 2014 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/53
Abstract
An arrangement for reducing the erratic operation of a non-volatile memory cell caused by the accumulation of holes at a specific location within the cell during the electrical erasing of the cell includes a layer of hole confinement material positioned at the specific location the holes accumulate for containing the holes in a specific area. The arrangement also includes an arrangement for removing the holes from the containment area. A method of reducing the erratic operation of a non-volatile memory cell caused by the accumulation of holes at a specific location within the cell during the electrical erasing of the cell includes the step of providing a layer of hole confinement material positioned at the specific location the holes accumulate for containing the holes in the layer of hole confinement material.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.