Digital processor and viterbi decoder having shared memory
US5432804A · kind A · utility
25Cited by
11References
9Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 16, 1993 |
| Grant date | Jul 11, 1995 |
| Priority date | — |
| Expiry date | Nov 16, 2013 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M13/6569
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An integrated circuit includes a digital signal processor (DSP) and an error correction co-processor (ECCP) that implements a Viterbi decoding function. The DSP and ECCP share a block of multi-port memory, typically by bus multiplexing a dual-port RAM. When the ECCP possesses the RAM, it inhibits the DSP from accessing that block of the RAM by asserting an EBUSY flag. This technique conserves and optimizes the RAM usage, allowing the DSP and ECCP to advantageously be formed on the same integrated circuit chip.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.