Digital phase comparator and phase-locked loop
US5432826A · kind A · utility
12Cited by
6References
8Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Aug 31, 1993 |
| Grant date | Jul 11, 1995 |
| Priority date | — |
| Expiry date | Aug 31, 2013 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/089
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A digital phase comparator measures the phase difference of two signals (S1, S3) from a third signal (S2), and calculates the difference. The zero crossing of the two signals respectively sets two flip-flops (11, 12). If both flip-flops are set, they are simultaneously reset with a delay. Each set flip-flop enables a corresponding counter (13, 14). An evaluation unit averages the counter outputs at major intervals. The phase comparator can be incorporated into a phase-locked loop.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.