Low frequency telecommunication digital network interface patch panel
US5432847A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Mar 29, 1994 |
| Grant date | Jul 11, 1995 |
| Priority date | — |
| Expiry date | Mar 29, 2014 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01R2107/00
- WIPO fieldElectrical machinery, apparatus, energy
- WIPO sectorElectrical engineering
Abstract
A low frequency telecommunication digital network interface patch panel 10 is described having the capability of terminating and providing front access to one-hundred-sixty-eight low frequency network elements 12 and 14 that generate low frequency signals between 1 and 3 Mbps. The panel has a housing with twenty-one adjacent modules; each module being one inch in width and having an upper set of wire-wrap pins 38 and a lower set of wire-wrap pins 40 that are spaced at one-quarter inch on center from each other. The pins 38, 40 are arranged in upper columns and lower columns that are vertically aligned with each other. The pins 38, 40 extend forward from a printed circuit board 60 through front module members 62 to ends 54 and rearward through rear module member 64 to wire-wrap terminal ends 56. The ends 56 are adapted for permanent termination with twisted wire pairs of the network elements. The forward front ends 64 are adapted to receive a female access plug 120 having four wire-wrap pin cavities 126. The printed circuit board 60 has a switch means 78 for operatively interconnecting a column 40 with a corresponding lower set of four pins 44. The female patch plug 120 includes a p…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.