Power control technique for a computer system to provide adjustable storage and non-storage access times and an adjustable processor idle time
US5432947A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | May 21, 1993 |
| Grant date | Jul 11, 1995 |
| Priority date | — |
| Expiry date | May 21, 2013 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A power control apparatus having a plurality of external devices and adapted to be used for a computer system and to reduce the power consumption in an idle state, the apparatus includes a processing unit for receiving a signal from at least one of the plurality of external devices and for outputting an instruction according to the received signal, a storage unit connected to the processing unit for temporary storing information and for accessing to the processing unit according to the instruction output from the processing unit, an interface unit connected to both the processing unit and the storage unit for controlling an interface between the processing unit and the storage unit, and an adjusting unit connected to the interface unit for adjusting a time proportion of an access cycle to a non-storage unit, for adjusting a time proportion in an operation of the processing unit to be stopped, and for adjusting an access to the storage unit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.