Inverted spacer transistor
US5434093A · kind A · utility
128Cited by
9References
25Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 10, 1994 |
| Grant date | Jul 18, 1995 |
| Priority date | — |
| Expiry date | Aug 10, 2014 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/0217
Abstract
A method for forming narrow length transistors by forming a trench in a first layer over a semiconductor substrate. Spacers are then formed within the trench and a gate dielectric is formed between the spacers at the bottom of the trench on the semiconductor substrate. The trench is then filled with a gate electrode material which is chemically-mechanically polished back to isolate the gate electrode material within the trench, and the first layer is removed leaving the gate dielectric, gate electrode and spacers behind.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.