Self-resetting CMOS off-chip driver
US5434519A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Oct 11, 1994 |
| Grant date | Jul 18, 1995 |
| Priority date | — |
| Expiry date | Oct 11, 2014 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/09429
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A self-resetting CMOS off-chip diver includes a first pair of complementary FETs connected in series to receive first and second complementary drive signals from an on-chip source. A latch is connected to an output of the first pair of complementary FETs for latching said drive signals. The first pair of complementary FETs in combination with the latch form a unique "pulse catcher" circuit capable of catching and latching short duration pulses characteristic of the self-resetting (SR) mode, providing the transfer between the SR mode and the output static mode. A low power three state static driver circuit is comprised of first and second pass gates connected to pass an output of the latch and a second pair of complementary FETs respectively connected to receive outputs of the first and second pass gates to generate a static output for driving a transmission line. Pull-up and pull-down devices are connected to respective inputs of the second pair of complementary FETs and controlled by the control means to provide a three state function output. The three state static circuit provides high speed data transfer with a high drive capability full swing signal output. An enable circuit im…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.