Two-transistor dynamic random-access memory cell having a common read/write terminal
US5434816A · kind A · utility
10Cited by
8References
2Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Jun 23, 1994 |
| Grant date | Jul 18, 1995 |
| Priority date | — |
| Expiry date | Jun 23, 2014 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/403
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A two transistor dynamic random access memory can be treated as a pair of voltage controlled elements which are reversibly controlled in a three step process. In the first step, a capacitance is charged on the controlling terminal of memory transistor. The second step entails isolating the charge on the capacitance of the controlling terminal. The third step entails providing a reversibly controlled voltage on the controlling terminal to further control the two memory transistors without altering the charge of the capacitance. This allows a non-destructive reading of the output of the stored information signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.