Throttling circuit for a data transfer system
US5434892A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Sep 16, 1994 |
| Grant date | Jul 18, 1995 |
| Priority date | — |
| Expiry date | Sep 16, 2014 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2205/126
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A data transfer system includes a buffer for storing data to be transferred out of the buffer and a register circuit coupled to the buffer for receiving the data from the buffer. The buffer generates a first indication signal when the buffer is almost empty. The buffer generates a second indication signal when the buffer is empty. The register circuit generates a request signal to receive the data from the buffer. The data transfer system further includes a throttling circuit coupled to the buffer and the register circuit for throttling data transmission to the register circuit from the buffer when the buffer generates the first indication signal and for stopping data transmission to the register circuit from the buffer when the buffer generates the second indication signal. The throttling circuit receives the first and second indication signals and the request signal. The throttling circuit maintains maximized data transfer rate between the buffer and the register circuit while immediately stopping the data transfer between the buffer and register circuit when the buffer is empty.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.