Methods and apparatus for creating a pending write-back controller for a cache controller on a packet switched memory bus employing dual directories
US5434993A · kind A · utility
Assignees
Inventors
Key dates
| Filing date | Nov 9, 1992 |
| Grant date | Jul 18, 1995 |
| Priority date | — |
| Expiry date | Nov 9, 2012 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0831
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A write-back cache control system having a pending write-back cache controller in a multiprocessor cache memory structure. The processor subsystems in the multiprocessor system are coupled together using a high-speed synchronous packet switching bus called a memory bus. Each processor subsystem has an associated cache control system. When a processor's cache control system does not have a required memory location in the cache memory, it broadcasts a memory request packet across the memory bus for the required data. If an owned cache line is being replaced, the cache control system copies the old cache line data to the pending write-back cache controller which is responsible for the write-backs of owned cache lines to main memory. The cache control system then transfers ownership of the old replaced cache line to the pending write-back controller. When the cache control system receives the new cache line information from the memory bus, it immediately replaces the cache line and allows the processing to continue. By buffering the old cache line in the pending write-back controller, the cache control system allows the new cache line to be requested before the old cache line is writte…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.