Barrier synchronization for distributed memory massively parallel processing systems
US5434995A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Dec 10, 1993 |
| Grant date | Jul 18, 1995 |
| Priority date | — |
| Expiry date | Dec 10, 2013 |
Classification
- Technology area (CPC F)Mechanical Engineering; Lighting; Heating
- CPC primaryF02B2075/027
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A barrier mechanism provides a low-latency method of synchronizing all or some of the processing elements (PEs) in a massively parallel processing system. The barrier mechanism is supported by several physical barrier synchronization circuits, each receiving an input from every PE in the processing system. Each PE has two associated barrier synchronization registers, in which each bit is used as an input to one of several logical barrier synchronization circuits. The hardware supports both a conventional barrier function and an alternative eureka function. Each bit in each of the barrier synchronization registers can be programmed to perform as either barrier or eureka function, and all bits of the registers and each barrier synchronization circuit functions independently. Partitioning among PEs is accomplished by a barrier mask and interrupt register which enables certain of the bits in the barrier synchronization registers to a defined group of PEs. Further partitioning is accomplished by providing bypass points in the physical barrier synchronization circuits to subdivide the physical barrier synchronization circuits into several types of PE barrier partitions of varying size an…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.