High-speed semiconductor integrated circuit device with reduced delay in gate-to-gate wiring
US5436573A · kind A · utility
13Cited by
6References
15Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 31, 1993 |
| Grant date | Jul 25, 1995 |
| Priority date | — |
| Expiry date | Aug 31, 2013 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A semiconductor integrated circuit device has a first wire for transmitting a first signal and a second wire adjacent to the first wire, for transmitting a second signal having the stronger probability of having an opposite phase to that of the first signal. A space between the first and second wires is wider than a standard wiring space, to reduce a delay in the operation speed of the device due to wiring capacitance produced between the first and second wires.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.