CMOS output pad driver with variable drive currents ESD protection and improved leakage current behavior
US5436578A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jul 14, 1993 |
| Grant date | Jul 25, 1995 |
| Priority date | — |
| Expiry date | Jul 14, 2013 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/998
Abstract
A configurable circuit for driving an integrated circuit output pad includes two differently-sized arrays of p-channel FETs and two arrays of differently-sized n-channel FETs for driving the pad. A circuit designer selects different ones of the FETs to produce a desired level of n-channel and p-channel drive at the pad. The nonselected p-channel FETs are maintained in a disabled condition by tieing them off to one side of a p-channel FET which is also connected to a n-type island in a substrate in which the circuit is formed. Electrostatic charge is drained from the gates of the disabled FETs through the n-type island when power is not applied to the integrated circuit thereby preventing failure of leakage tests. The nonselected n-channel FETs are similarly tied to one side of an n-channel FET which in turn is tied to a p-type island to achieve the same purpose for the n-channel FETs. A photolithographic mask embodying a configurable circuit is provided to a designer who utilizes a CAD program to lay down polysilicon connections to select the drive transistors and disable the nonselected transistors.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.