Method and apparatus for testing frequency symmetry of digital signals
US5436927A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Mar 31, 1993 |
| Grant date | Jul 25, 1995 |
| Priority date | — |
| Expiry date | Mar 31, 2013 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R23/005
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A first and a second input generating circuits, a first and a second set of counters, and a first and a second comparison circuits are provided to test whether the frequencies of a first and a second periodic digital signal are symmetric. The first and second input generating circuits generate enable inputs for the first and second sets of counters using the first and second digital signals respectively. The first and second sets of counters count the first and second digital signals while the enable inputs are provided. The first comparison circuit monitors the first set of counters, and stops both input generating circuits from providing further enable inputs to both sets of counters, after the first set of counters reaches a predetermined level, thereby stopping both sets of counters from further counting. The second comparison circuit monitors the second set of counters, and issues a control signal indicating the first and second digital signals are symmetric to each other in frequency, if the second set of counters also stops substantially at the predetermined level, i.e. within an acceptable threshold.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.