Multi-phase clock generator and multiplier
US5436939A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Oct 3, 1994 |
| Grant date | Jul 25, 1995 |
| Priority date | — |
| Expiry date | Oct 3, 2014 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K3/0315
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A multiphase clock generator which exhibits frequency stability in the presence of power supply noise. The clock generator of the present invention includes a phase detector for generating a phase error signal in response to the phase difference between an input signal and a recovered clock signal. A phase-locked feedback loop is operative to synthesize a recovered clock signal in response to the phase error signal. Included within the feedback loop is a differential ring oscillator disposed to provide first and second phase-shifted output signals at first and second output ports. The addition of a combination network to the multiphase clock generator of the present invention allows a multiplied clock signal to be derived from an input signal. Specifically, the phase-locked feedback loop 18 included within the clock multiplier of the present invention provides a plurality of sequentially phase-shifted waveforms at a first multiple of the frequency of the input signal. The phase-shifted waveforms are then combined into the output clock signal at a second multiple of the frequency of the input clock signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.