Simulation using compiled function description language
US5437037A · kind A · utility
54Cited by
3References
10Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Jun 7, 1993 |
| Grant date | Jul 25, 1995 |
| Priority date | — |
| Expiry date | Jun 7, 2013 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/33
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A simulation program conversion method and system is provided. The original simulation program is written by a function description language, such as Verilog-HDL, using a text editor, and, then, the original simulation program is converted into an executable program using a programming language, such as the C language, so that the simulation program may be compiled before execution. The speed of execution of the simulation program is significantly improved.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.