Arrangement of DMA, interrupt and timer functions to implement symmetrical processing in a multiprocessor computer system
US5437042A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Oct 2, 1992 |
| Grant date | Jul 25, 1995 |
| Priority date | — |
| Expiry date | Oct 2, 2012 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/32
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An arrangement of direct memory access (DMA), interrupt and timer functions in a multiprocessor computer system to allow symmetrical processing. Several functions which are considered common to all of the CPUs and those which are conveniently accessed through an expansion bus remain in a central system peripheral chip coupled to the expansion bus. These central functions include the primary portions of the DMA controller and arbitration circuitry to control access of the expansion bus. A distributed peripheral, including a programmable interrupt controller, multiprocessor interrupt logic, nonmaskable interrupt logic, local DMA logic and timer functions, is provided locally for each CPU. A bus is provided between the central and distributed peripherals to allow the central peripheral to broadcast information to the CPUs, and to provide local information from the distributed chip to the central peripheral when the local CPU is programming or accessing functions in the central peripheral.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.