Controlled delay digital clock signal generator
US5438291A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Dec 16, 1993 |
| Grant date | Aug 1, 1995 |
| Priority date | — |
| Expiry date | Dec 16, 2013 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K5/082
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Controlled delay digital clock signal generator, characterised in that it comprises means (I5, I6, I7, I8, I9, I10, IT7, IT8, IT9, IT10, C4) to generate from a clock signal (CK) and its complementary signal (CKB) a ramp signal comprising at least two segments of positive slope and at least two segments of negative slope, means (I1, I2, IT1, IT2, IT3, C2, CET1T2, AMPLI, I3, I4, IT4, IT5, IT6, C3, CET3T4, AMPL2) for separate control of the slopes of the said segments, means with trigger circuits (AMPLO) for converting the ramp signal (RAMP) into a square signal (CKQ) means (NO0, A0, A1, NO1) for achieving the logic combinations of the delayed square clock signal (CKQ) resulting from the conversion with the clock signal (CK) and the clock complementary clock signal (CKB) of the said clock signal to obtain as many delayed digital clock signals as the ramp signal has segments of different slopes.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.