Digital frequency multiplier utilizing digital controlled oscillator
US5438300A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Apr 1, 1994 |
| Grant date | Aug 1, 1995 |
| Priority date | — |
| Expiry date | Apr 1, 2014 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/0997
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A frequency multiplier includes a ring oscillator having a number of logic gates arranged in a plurality of rings. Control inputs enable the selection of individual gates so as to connect them into the ring or, conversely, remove them from the ring. As additional gates are removed, the combined delay imposed by the gates remaining in the ring is reduced and the frequency of the oscillator increases. A variable delay element, preferably a group of tri-state inverters connected in parallel, is connected between two of the gates. The oscillator is fine tuned by controlling the delay inserted by the variable delay element. The frequency multiplier also includes a frequency comparator. A reference frequency is passed through a divide-by-K unit and the output of the ring oscillator is passed through a divide-by-N unit, N being greater than K. The frequency multiplier is coarse-tuned by progressively removing additional gates from the ring oscillator, and then fine-tuned by increasing the delay imposed by the variable delay element. At the conclusion of coarse and fine tuning, the frequency multiplier is locked at a frequency which closely approximates a reference frequency multiplied by …
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.