Nonvolatile memory with volatile memory buffer and a backup power supply system
US5438549A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Feb 28, 1994 |
| Grant date | Aug 1, 1995 |
| Priority date | — |
| Expiry date | Feb 28, 2014 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C5/141
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory device that resides on a single substrate includes a nonvolatile memory array. Control circuitry is coupled to the memory array for controlling memory operations with respect to the memory array. A volatile memory buffer is coupled to the control circuitry for buffering data that is to be written into the memory array. The control circuitry fetches the data from the memory buffer to store in the memory array. A power supply control circuit is provided for detecting loss of a power supply applied to the memory buffer and for coupling a backup power supply to the memory buffer when the power supply is disconnected from the memory buffer such that data integrity of the memory device is maintained.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.