Shared memory bus system for arbitrating access control among contending memory refresh circuits, peripheral controllers, and bus masters
US5438666A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jun 30, 1992 |
| Grant date | Aug 1, 1995 |
| Priority date | — |
| Expiry date | Jun 30, 2012 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/364
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An arbitration system for a shared address, data and control bus provides burst mode operations for transferring data between a peripheral device and memory via a bus master. The arbitration system is responsive to high priority bus activities, such as memory refresh cycles and DMA cycles to temporarily transfer control of the shared bus from the bus master to a circuit controlling the high priority activity. After the high priority activity is completed, the arbitration system returns control of the shared bus to the bus master so that the associated peripheral device may continue operating in the burst mode. This transfer of control occurs without requiring the time overhead of arbitrating priority between bus masters having active bus requests. The arbitration system further includes timing circuits to assure that a bus master transferring data in the burst mode does not retain control of the shared bus for an excessive amount of time.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.