Antifuse with double via contact and method of manufacture therefor
US5440167A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Feb 23, 1994 |
| Grant date | Aug 8, 1995 |
| Priority date | — |
| Expiry date | Feb 23, 2014 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The present invention provides for a method of forming an antifuse in an integrated circuit having a first insulating layer on a semiconductor substrate. The method comprises forming a first metal interconnection layer on the first insulating layer; forming a programming layer on the first metal interconnection line; forming a relatively thin, second insulating layer over the programming layer; forming a first aperture through the second insulating layer where the antifuse is to be located to expose a portion of the programming layer; forming a barrier metal layer on the second insulating layer and in said first aperture to contact the portion of said programming layer; forming a relatively thick, third insulating layer on the barrier metal layer; forming a second aperture to expose a portion of the barrier metal layer; and forming a second metal interconnection layer on the third insulating layer and in the second aperture to contact the portion of the second barrier metal layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.