Digital filtering circuit operable as a three-stage moving average filter
US5440503A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Feb 15, 1994 |
| Grant date | Aug 8, 1995 |
| Priority date | — |
| Expiry date | Feb 15, 2014 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03H17/0657
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
In a digital filtering circuit for converting an input data signal (a) of a sampling frequency f.sub.s into an output data signal (OUT) of an oversampling frequency Nf.sub.s which is N times the sampling frequency f.sub.s. The digital filtering circuit comprises a combination of a calculating circuit (30), and first and second integrating circuits (40, 50). The first integrating circuit (40) integrates a calculated signal (d) in synchronism with the oversampling frequency Nf.sub.s to produce a first integration result signal (b) and a first delayed signal (e). The second integrating circuit (50) integrates the first delayed signal (e) in synchronism with the oversampling frequency Nf.sub.s to produce a second integration result signal (c) and a second delayed signal (f) as the output data signal (OUT). The calculating circuit (30) carries out a predetermined calculation on the input data signal (a), the first integration result signal (b), and the second integration result signal (c) in synchronism with the sampling frequency f.sub.s to produce the calculated signal (d). The predetermined calculation is represented by an equation as follows: EQU d={a-c-(1+3N)b/2}/N.sup.2.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.