Method and apparatus for simuilataneous long writes of multiple cells of a row in a static ram
US5440524A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Feb 1, 1994 |
| Grant date | Aug 8, 1995 |
| Priority date | — |
| Expiry date | Feb 1, 2014 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/418
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A multiple column select circuit enables simultaneous selection of multiple columns of a static RAM to allow a "long write" test for leakage defects whereas a fewer number of columns are selected during normal operation of the static RAM. In one embodiment, a multiple column select circuit includes an inverter, the output lead of which is coupled to the pull-up circuits of each respective column of the static RAM. When a multiple column select input signal is asserted, a supply voltage supplied to each of the pull-up circuits by the output lead of the inverter switches from V.sub.DD to ground potential thereby simultaneously selecting multiple columns of the static RAM. In another embodiment, a multiple column select circuit drives each individual column select line of the memory. When a multiple column select input signal is asserted, each individual column select line is asserted, thereby selecting all columns. When the multiple column select input signal is not asserted, a column addressing circuit controls the voltages on the column select lines through the multiple column select circuit to select only one column.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.