Frame synchronizing circuit for frame synchronization of digital signals
US5442405A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Dec 22, 1993 |
| Grant date | Aug 15, 1995 |
| Priority date | — |
| Expiry date | Dec 22, 2013 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04N7/56
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A frame synchronizing apparatus is disclosed which includes a serial-parallel converter for converting input serial data into parallel data of a plurality of channels; a plurality of intra-channel synchronization detecting circuits each for detecting a synchronization pattern and a pseudo-synchronization pattern in one channel, and generating a channel synchronization detect signal and a pseudo-synchronization detect signal in one channel; a plurality of bit-shift error pattern detecting circuits each for detecting a bit-shift error pattern in one channel, and generating a bit-shift error pattern signal in one channel; a synchronization/bit-shift error detecting circuit for detecting a synchronization between channels and specifying the amount of erroneously shifted bits, and generating a frame synchronization detect signal and bit-shift error detect signals; and a bit-shift signal generating circuit for calculating the number of erroneously shifted bits in the serial-parallel converter based on the bit-shift error detect signals and the bit-shift error pattern signals, and generating a bit-shift signal to be supplied to the serial-parallel converter, whereby bits of the calculated…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.