Parallel processing circuit and a digital signal processer including same
US5442580A · kind A · utility
11Cited by
4References
16Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | May 25, 1994 |
| Grant date | Aug 15, 1995 |
| Priority date | — |
| Expiry date | May 25, 2014 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F7/5443
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A parallel processing circuit and a digital signal processor employing such a parallel circuit employs a plurality of identical multiply and accumulate (MAC) processing units. Two input signals are supplied to each of the MAC processing units. In one embodiment, a delay or a shift register delays one of the input digital signal from one MAC to another MAC. A plurality of different processed signals can be generated simultaneously based upon the supplied input digital signals, greatly increasing processing capability without increasing clock speed or increasing bandwidth access to a memory.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.