Compensated analog multipliers
US5442583A · kind A · utility
6Cited by
5References
21Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 14, 1993 |
| Grant date | Aug 15, 1995 |
| Priority date | — |
| Expiry date | May 14, 2013 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06G7/16
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The multiplier which includes built-in adjustments to improve circuit performance. More specifically, the multiplier is a compensated multiplier to increase the accuracy and precision of computation using analog very large scale integrated (VLSI) circuits and consists of adjustable parameters which allow for the improvement of the linear range of behavior as well as the cancellation of input offsets. A differential multiplier is further described in which adjustable parameters in addition to the four inputs to the multiplier compensate for offsets and non-linearities to result in a highly accurate analog multiplier.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.