Digitally phase modulated clock inhibiting reduced RF emissions
US5442664A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Dec 20, 1993 |
| Grant date | Aug 15, 1995 |
| Priority date | — |
| Expiry date | Dec 20, 2013 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K7/06
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A modulator for a clock pulse generator receives clock pulses from a clock pulse source, which clock pulses exhibit a reference phase. Delay circuitry is connected to the clock pulse source and includes n tap connections, each connection providing a clock pulse that is delayed by a different phase delay from the reference phase. A multiplexer is connected to each of the n tap connections and provides an output manifesting the clock pulses. A selector circuit controls the multiplexer to sequentially connect any sequence of different ones of the n tap connections to the multiplexer's output, whereby the output manifests a series of clock pulses which have different phase displacements from the reference phase.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.