Architecture of output switching circuitry for frame buffer
US5442748A · kind A · utility
Assignees
Inventors
Key dates
| Filing date | Oct 29, 1993 |
| Grant date | Aug 15, 1995 |
| Priority date | — |
| Expiry date | Oct 29, 2013 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG09G2360/126
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A frame buffer including a plurality of array planes of memory cells, row decoding circuitry for selecting rows of memory cells in each of the array planes to be accessed, column decoding circuitry for selecting columns of memory cells in each of the array planes to be accessed, a plurality of bitlines associated with the columns of memory cells of each array plane, each of the bitlines connecting to a column of memory cells and including a bitline sensing amplifier and a column select switch for providing access to the memory cells of that column of the array plane, a plurality of output sense amplifiers adapted to be connected to a selected number of bitlines in an array plane by closing of particular ones of the column select switches in the bitlines, first apparatus for providing output signals from the plurality of output sense amplifiers associated with each array plane to a data bus, and second apparatus for providing output signals from the plurality of output sense amplifiers associated with each array plane to a shift register.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.