Triple port cache memory
US5442770A · kind A · utility
143Cited by
12References
10Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Jun 11, 1993 |
| Grant date | Aug 15, 1995 |
| Priority date | — |
| Expiry date | Jun 11, 2013 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0886
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Cache memory input/output apparatus that allows transfer of a single data word and transfer of consecutive sequences of data words in a row of memory, using two independent serial ports and a random access port whose actions are controlled in part by a memory address signal. Data transferred by the serial ports are double buffered, each serial port having two independent registers; and the two registers associated with a serial port may be ganged together to transfer data sequences having word lengths from 16, or multiples thereof, up to arbitrary multiples of the length of a row of data words.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.